Microelectronic circuits are very complex, highly integrated circuits and are designed today with the aid of electronic design automation (EDA) software. The EDA software offers support in the production of circuit designs, for example in the semi-automated development of integrated circuits and the production of a layout (mask data) for a semiconductor chip. A designer specifies the microelectronic circuit in the EDA software. The EDA software subsequently converts the specification into a circuit diagram and creates the layout for the microelectronic circuit.
In view of the increasing integration of microelectronic circuits, the integrity of the signals in the microelectronic circuit becomes an important factor. The integrity of the signals depends among other things on the electric signal-to-noise ratio due to electrical noise in the microelectronic circuit. One of the disturbance sources for the electrical noise is variations in the supply line voltages due to the switching of elements in the microelectronic circuit. The magnitude of this electric noise depends on the number of simultaneously switched elements in the electronic circuit, their size, capacities and positions on the semiconductor chip and the packing density of the elements on the chip.
In order to reduce this electrical noise, so-called decoupling capacitors are incorporated into the microelectronic circuit on the chip. These decoupling capacitors are preferably positioned in the vicinity of the disturbance sources, for example switching elements. The decoupling capacitors dampen the high-frequency electric noise in the supply lines. It is known that the most effective position for the decoupling capacitors is below the switching elements or the supply lines.
Various solutions for positioning the decoupling capacitors are known from the state of the art. For example, the U.S. Pat. No. 7,033,883 (Faraday Technology Corp.) discloses a method for positioning the decoupling capacitors in an integrated circuit by detecting free space on a chip. The decoupling capacitors are integrated in the free spaces.
The U.S. Pat. No. 7,709,301 (Texas Instruments) also teaches a microelectronic circuit with decoupling capacitors. This patent teaches the production of two adjacent decoupling capacitors with an electric layer between the two decoupling capacitors.
The U.S. Pat. No. 6,898,769 (IBM) teaches a method and a system for optimizing the position and the size of decoupling capacitors on a semiconductor chip. Logical cells are positioned in a first layout of the microelectronic circuit and the decoupling capacitors are inserted in the empty space between neighboring cells.
The U.S. Pat. No. 6,618,843 discloses a method for analyzing decoupling capacities in a microelectronic circuit. This method includes, among other things, an analysis of the number of decoupling capacitors and their spacing from the switching elements in the microelectronic circuit. The method also takes account of the orientation and the size of the individual switching elements.
The U.S. Patent Application Publication No. 2014/0282340 (Freescale) discloses a method for positioning the decoupling capacitors in a microelectronic circuit, which firstly includes an analysis of the circuit design without the decoupling capacitors with a simulation of variations in the microelectronic circuit. On the basis of this analysis the demand for decoupling capacity is ascertained which is taken into account for observing the specifications for the supply line. A decoupling capacitor for these specifications is then determined and incorporated into the circuit.
The German Patent No. DE 103 39 283 B9 describes a method for designing re-design capable integrated circuits in which fill cells represent replacement logic devices. It is possible to correct logic malfunctions of the integrated circuit caused by an error in the design, for example by incomplete verification, with the aid of a modified wiring. The re-design capability is achieved by filling the area of the filling cells in the place and route design step with additional semiconductor components. These represent spare logic gates, which are used, if necessary, during a re-design, in order to correct malfunctions of the logic modules assigned to the logic cells. The necessary iteration cycle for logic correction is therefore limited to the BEOL (Back End Of Line) section of the manufacturing process.
The U.S. Pat. No. 6,618,847 B1 (STMicroelectronics, Inc.) describes the optimization of the electrical properties of an integrated circuit (IC) by modifying the physical layout of the IC. Specifically, U.S. Pat. No. 6,618,847 B1 determines when portions or regions of the IC relating to different standard cells are under-utilized in the IC design. U.S. Pat. No. 6,618,847 B1 includes appropriate electrical components in such underused areas to increase electrical power, such as stabilizing the energy delivered to various logic areas of the IC, such as macros. U.S. Pat. No. 6,618,847 B1 describes that capacitors are inserted into the filling cells 25, thereby producing gate capacitors in the spaces 40.
There is a need to increase the decoupling capacitance of a microelectronic circuit.